Fan-out

Wafer-level fan-out (WLFO) and fan-out panel-level-package (FO-PLP) are designed to provide increased space for I/O’s, while maintaining a reduced footprint and profile, for both single and multi-die applications at a lower cost.

Smaller dimensions, denser and more numerous redistribution layers, and smaller defects make fan-out inspection challenging. Metrology of die shift on fan-out reconstructed wafers constitutes input that is needed for other process steps, including lithography and plating.

Camtek’s technology provides dedicated inspection and metrology capabilities that address the challenging fan-out process and specifically enable our systems to inspect wafers with RDLs of 2-micron line/space.

Our systems provide surface inspection capabilities and keep track of unique metrology data that address die placement and alignment between the layers, as well as advanced handling solutions designed to deal with warped wafers.

Computer Aided Design (CAD) based inspection offered by Camtek’s systems compares the image acquisition of the dies on the reconstructed wafer with the CAD data used in fabricating the wafer. Using CAD as a reference for detecting the reconstructed wafers solves alignment issues that might otherwise arise.

• RDL inspection and metrology
• Multi-layer RDL inspection
• Multiple optics settings for all steps and all defect types
• 3D height and co-planarity measurement
• Die shift and rotation measurement
• CAD-based detection

• Camtek’s unique white light triangulation sensor
• Advanced processing engines for defect inspection and metrology
• High-resolution 3D confocal sensor
• Light interferometry technology for 3D applications
• CSI (Clear Sight Illumination) enabling the inspection of the top RDL layer in multi-layer RDLs
• CAD-based detection